Saturn Launch Vehicle Digital Computer

It was used in conjunction with the Launch Vehicle Data Adaptor (LVDA) which performed signal conditioning from the sensor inputs to the computer from the launch vehicle.

The LVDC was capable of executing 12190 instructions per second. For comparison, as of 2022, researchers at the University of California created a chip capable of running at 1.78 trillion instructions per second, 146 million times faster. • Illustration — LVDC with the front logic section removed, displaying eight memory assemblies. • Illustration — LVDC memory module closeup Its master clock ran at 2.048 MHz, but operations were performed bit-serially, with 4 cycles required to process each bit, 14 bits per instruction phase, and 3 phases per instruction, for a basic instruction cycle time of 82 μs (168 clock cycles) for a simple add. A few instructions (such as multiply or divide) took several multiples of the basic instruction cycle to execute. Memory was in the form of 13-bit syllables, each with a 14th parity bit. Instructions were one syllable in size, while data words were two syllables (26 bits). Main memory was random access magnetic core, in the form of 4,096-word memory modules. Up to 8 modules provided a maximum of 32,768 words of memory. Ultrasonic delay lines provided temporary storage. For reliability, the LVDC used triple-redundant logic and a voting system. The computer included three identical logic systems. Each logic system was split into a seven-stage pipeline. At each stage in the pipeline, a voting system would take a majority vote on the results, with the most popular result being passed on to the next stage in all pipelines. This meant that, for each of the seven stages, one module in any one of the three pipelines could fail, and the LVDC would still produce the correct results. The result was an estimated reliability of 99.6% over 250 hours of operation, which was far more than the few hours required for an Apollo mission. With four memory modules, giving a total capacity of 16,384 words, the computer weighed 72.5 lb, was 29.5 x in size and consumed 137W. • Illustration — Apollo Saturn V analog Flight Control Computer Unit FCC The LVDC communicated digitally with a Launch Vehicle Data adapter (LVDA). The LVDA converted analog-to-digital and digital-to-analog with a Flight Control Computer (FCC). The FCC was an analog computer.

LVDC instruction words were split into a 4-bit opcode field (least-significant bits) and a 9-bit operand address field (most-significant bits). This left it with sixteen possible opcode values when there were eighteen different instructions: consequently, three of the instructions used the same opcode value, and used two bits of the address value to determine which instruction was executed. Memory was broken into 256-word "sectors". 8 bits of the address specified a word within a sector, and the 9th bit selected between the software-selectable "current sector" or a global sector called "residual memory". The eighteen possible LVDC instructions were: • Instruction || Opcode || Function • HOP — 0000 — Transfer execution to a different part of the program. Unlike a modern 'jump' instruction the operand address did not actually specify the address to jump to, but pointed to a 26-bit 'HOP constant' which specified the address. • MPY — 0001 — Multiply the contents of the memory location specified in the operand address by the contents of the accumulator register. This instruction took four instruction cycles to complete, but didn't stall program execution, so other instructions could execute before it finished. The result was left in a known register. • SUB — 0010 — Subtract the contents of the memory location specified in the operand address from the accumulator register. • DIV — 0011 — Divide the contents of the memory location specified in the operand address into the accumulator. This instruction took eight instruction cycles to complete, but didn't stall program execution. • TNZ — 0100 — Transfers instruction execution to the operand address specified if the accumulator contents are not zero. • MPH — 0101 — Multiply the contents of the memory location specified in the operand address by the contents of the accumulator register. Unlike MPY, this instruction does halt execution until the multiplication is complete. • AND — 0110 — Logically AND the contents of the accumulator with the contents of the memory location specified in the operand address. • ADD — 0111 — Add the contents of the memory location specified in the operand address to the accumulator register. • TRA — 1000 — Transfer execution to the memory location specified in the operand address. The address is within the current instruction sector; the 9th (residual) bit of the operand selects the syllable. • XOR — 1001 — Logically XOR the contents of the accumulator with the contents of the memory location specified in the operand address. • PIO — 1010 — Process input or output: communicate with external hardware via the Data Adapter. "The low order address bits, A1 and A2, determine whether the operation is an input or output instruction. The high order address bits, A8 and A9, determine whether the data contents are transferred from the main memory, residual memory or accumulator." • STO — 1011 — Store the contents of the accumulator register in the memory location specified in the operand address. • TMI — 1100 — Transfer execution to the operand address specified if the accumulator contents are negative. • RSU — 1101 — Contents of the accumulator are subtracted from the contents of the memory location specified in the operand address, and the result left in the accumulator. • SHR — 01 1110 — Contents of accumulator are shifted by up to two bits, based on a value in the operand address. This instruction can also clear the accumulator if the operand address bits are zero. • CDS — x0 1110 — Change data sector. • EXM — 11 1110 — Transfer execution to one of eight addresses dependent on the operand address, which also specifies modifications to the operand address of the next instruction before it is executed. • CLA — 1111 — (Clear accumulator and) load memory.

In flight the LVDC ran a major computation loop every 2 seconds for vehicle guidance, and a minor loop 25 times a second for attitude control. The minor loop is triggered by a dedicated interrupt every 40 ms and takes 18 ms to run. Unlike the Apollo Guidance Computer software, the software which ran on the LVDC seems to have vanished. While the hardware would be fairly simple to emulate, the only remaining copies of the software are probably in the core rope memory of the Instrument Unit LVDCs of the remaining Saturn V rockets on display at NASA sites.

The LVDC could also respond to a number of interrupts triggered by external events. For a Saturn IB these interrupts were: • LVDC Data Word Bit || Function • 1 — Internal to LVDC • 2 — Spare • 3 — Simultaneous Memory Error • 4 — Command Decoder Interrupt • 5 — Guidance Reference Release • 6 — Manual Initiation of S-IVB Engine Cutoff • 7 — S-IB Outboard Engines Cutoff • 8 — S-IVB Engine Out • 9 — RCA-110A Interrupt • 10 — S-IB Low Fuel Level Sensors Dry • 11 — RCA-110A Interrupt For a Saturn V these interrupts were: • LVDC Data Word Bit || Function • 1 — Minor Loop Interrupt • 2 — Switch Selector Interrupt • 3 — Computer Interface Unit Interrupt • 4 — Temporary Loss Of Control • 5 — Command Receiver Interrupt • 6 — Guidance Reference Release • 7 — S-II Propellant Depletion/Engine Cutoff • 8 — S-IC Propellant Depletion/Engine Cutoff • 9 — S-IVB Engine Out • 10 — Program Recycle (RCA-110A Interrupt) • 11 — S-IC Inboard Engine Out • 12 — Command LVDA/RCA-110A Interrupt

The LVDC was approximately 30 in wide, 12.5 in high, and 10.5 in deep and weighed 72.5 lb. The chassis was made of magnesium-lithium alloy LA 141, chosen for its high stiffness, low weight, and good vibration damping characteristics. The chassis was divided into a 3 x 5 matrix of cells separated by walls through which coolant was circulated to remove the 138 watts of power dissipated by the computer. Slots in the cell walls held "pages" of electronics. The decision to cool the LVDC by circulating coolant through the walls of the computer was unique at the time and allowed the LVDC and LVDA (part-cooled using this technique) to be placed in one cold plate location due to the three dimensional packaging. The cold plates used to cool most equipment in the Instrument Unit were inefficient from a space view although versatile for the variety of equipment used. The alloy LA 141 had been used by IBM on the Gemini keyboard, read out units, and computer in small quantities and the larger frame of the LVDC was produced from the largest billets of LA 141 cast at the time and subsequently CNC machined into the frame. A page consisted of two 2.5 - boards back to back and a magnesium-lithium frame to conduct heat to the chassis on low power pages and magnesium-aluminun-zinc on higher power pages. The 12-layer boards contained signal, power, and ground layers and connections between layers were made by plated-through holes. The plated-through holes were deliberately placed below the unit logic devices (ULD) to help conduct heat from the devices to the metal frames and thus the coolant walls. Up to 35 alumina squares of 0.3 x could be reflow soldered to a board. These alumina squares had conductors silk screened to the top side and resistors silk-screened to the bottom side. Semiconductor chips of 0.025 x, each containing either one transistor or two diodes, were reflow soldered to the top side. The complete module was called a unit logic device. The unit logic device (ULD) was a smaller version of IBM's Solid Logic Technology (SLT) module, but with clip connections. Copper balls were used for contacts between the chips and the conductive patterns. The hierarchy of the electronic structure is shown in the following table. LVDC electronic packaging • Level||Component||Material||IBM term • 1 — Transistor, diode — 0.025 x silicon — - • 2 — Up to 14 transistors, diodes and resistors — 0.3 x alumina — ULD (Unit Logic Device) • 3 — Up to 35 ULDs — 2.5 x printed circuit board — MIB (Multilayer Interconnection Board) • 4 — Two MIBs — Magnesium-lithium frame — Page

• Illustration — MSFC officials, including Wernher von Braun (on left) looking at an LVDC • Illustration — Computer, partially disassembled • Illustration — Eight toroid memory assemblies, collectively referred to as core memory